Phase change memory is a memory device which typically uses a chalcogenide material for the memory elements. A memory element is the unit that actually stores information. In operation, the phase change memory stores information on the memory element by changing the phase of the memory element between amorphous and crystalline phases. The chalcogenide material may exhibit either a crystalline or an amorphous phase, exhibiting a low or high conductivity. Generally, the amorphous phase has a low conductivity (high impedance) and is associated with a reset state (logic zero) and the crystalline phase has a high conductivity (low impedance) and is associated with a set state (logic one). The memory element may be included in a memory cell that also includes a selector, i.e., a select device coupled to the memory element. The select devices are configured to facilitate combining a plurality of memory elements into an array.
Phase change memory cells may be arranged in a cross-point memory array including row address lines and column address lines arranged in a grid. The row address lines and column address lines, called word lines (WLs) and bit lines (BLs), respectively, cross in the formation of the grid and each memory cell is coupled between a WL and a BL where the WL and BL cross (i.e., cross-point). It should be noted that row and column are terms of convenience used to provide a qualitative description of the arrangement of WLs and BLs in cross-point memory.
A memory cell may be selected by applying bias voltages to the WL and BL that cross at the memory cell. A resulting memory cell differential bias voltage across the memory cell is configured to be greater than a threshold select voltage for the memory cell. For a read operation, the threshold select voltage is generally greater than a maximum set voltage and less than a minimum reset voltage. For a write operation, i.e., programming operation, the threshold select voltage is generally greater than a maximum reset voltage.
In a read operation, the differential bias voltage across the memory element is configured to be greater than a maximum set voltage and less than a minimum reset voltage for the memory element. In response, the target memory element may or may not “snap back”, depending on whether the memory element is in the crystalline state (set) or the amorphous state (reset). Snap back is a property of the composite memory element that results in an abrupt (e.g., on the order of tens of picoseconds) increase in conductivity (and corresponding decrease in resistance) of the memory element. Sense circuitry, coupled to the memory element, is configured to detect the presence or absence of snap back in a sensing time interval. The presence of snap back may then be interpreted as a logic one and the absence of snap back as a logic zero.
During a programming operation, the differential bias voltage may be maintained across the memory cell for a first time period sufficient to cause the memory element to snap back. Current through the memory element may then be controlled for a second time period to transition the memory element from the amorphous state to the crystalline state or from the crystalline state to the amorphous state.
Although the following Detailed Description will proceed with reference being made to illustrative embodiments, many alternatives, modifications, and variations thereof will be apparent to those skilled in the art.